The CAD flow for implementing an electronic circuit design on a programmable logic device (PLD) such as a field-programmable gate array (FPGA) generally includes synthesizing a high-level specification of a design into a logic network, optimizing the original logic network, technology mapping the optimized network to logical abstractions of the programmable logic resources that are available on the PLD, and then placing and routing the mapped network on actual instances of the programmable logic resources of the PLD. At various stages of the CAD flow the logic circuit may be optimized for circuit area, number of logic blocks, circuit delay, power and/or routability.
In an example optimization, after the mapped network has been placed and routed the placed-and-routed network may be analyzed in order to improve some desired characteristic of the implemented design. For example, in an FPGA implementation power consumption may be reduced by changing the logic functions implemented by individual lookup tables (LUTs) without changing the overall function of the design. Boolean functional flexibility (or “Boolean flexibility” for short) refers to the ability to change the logic functionality or connectivity of a part of a logic circuit without affecting the functionality of the overall circuit. The Boolean flexibility of those LUTs for which the logic functions may be changed without changing the function of the design is used to improve the placed-and-routed design.
It would be desirable, therefore, to improve the CAD flow to provide further opportunities to optimize an electronic circuit design.